1. Field of the Invention
The present invention relates to a layout of an integrated circuit, and more particularly, to a layout of an integrated circuit capable of saving layout area.
2. Description of the Prior Art
With continued scaling-down of semiconductor integrated circuit (IC) device dimensions, not only are channel lengths being shortened, gate oxide layers becoming thinner, and junction depths getting shallower, but dopant concentrations are rising in deep submicron CMOS processes. All of these processes make IC products more susceptible to damage from electrostatic discharge (ESD). Consequently, more effective ESD protection circuits need to be built on-chip to discharge ESD-induced currents, and hence protect the IC against any ESD-related damage. In short, ESD robustness for IC products needs to be improved. To make an effective ESD protection circuit, an adequate ESD protection device must first be designed and manufactured into the ESD protection circuit. A very direct and effective way to increase the discharge path for ESD-induced current is enlarging the area of the ESD protection device. However, the chip area occupied by the ESD protection device should not be excessive, lest the ESD protection device prevent further size reductions to the chip.
Please refer to FIG. 1. FIG. 1 is a diagram of an ESD protection circuit according to the prior art. The ESD protection circuit 10 comprises a PMOS transistor 12, a resistor 14, and a capacitor 16. The resistor 14 is coupled between the gate and the source of the transistor 12. The capacitor 16 is coupled between the gate and the drain of the transistor 12. The resistor 14 and the capacitor 16 form a resistor-capacitor network (RC network). The source of the transistor 12 is coupled to a power supply, and the drain of the transistor 12 is coupled to a ground. When an electrostatic waveform occurs at the power supply, because of the signal delay effect due to the RC network, the rising rate of the voltage at node V1 is slower than the rising rate of the voltage at the power supply. Thus, a voltage difference occurs between the node V1 and the power supply. At the same time, the same voltage difference occurs between the transistor 12 and the power supply. When this voltage difference is greater than the threshold voltage of the transistor 12, the transistor 12 will turn on. Thus, the ESD protection circuit 10 can provide an ESD current path to avoid damage due to the current flowing into the internal circuits of an integrated circuit when the ESD event occurs. In addition, the ESD protection circuit can be formed with an NMOS transistor, and the operation of the ESD protection circuit formed with the PMOS transistor is similar to the ESD protection circuit 10.
Please refer to FIG. 2 and FIG. 3. FIG. 2 is a diagram of a first layout of the ESD protection circuit in FIG. 1 according to the prior art. FIG. 3 is a diagram of a second layout of the ESD protection circuit in FIG. 1 according to the prior art. As shown in FIG. 2, the transistor 12 is formed with a first poly-silicon layer 24 located above a diffusion layer 22. The capacitor 16 is formed with a second poly-silicon layer 26 located above the first poly-silicon layer 24. The resistor 14 is formed with the second poly-silicon layer 26. According to semiconductor processes, the diffusion layer 22, the first poly-silicon layer 24, and the second poly-silicon layer 26 are conductive layers, and each conductive layer is isolated by an oxide layer. Thus, each conductive layer is coupled with a contact window 28. In addition, the ESD protection circuit 10 has a pickup ring in the surroundings, and the pickup ring is formed with the diffusion layer 22. In order to release a large current, the transistor 12 of the ESD protection circuit 10 is formed with multiple bars of the first poly-silicon layer 24, and each bar of the first poly-silicon layer 24 is coupled with a metal layer (not shown). In FIG. 2, the transistor 12 formed with two bars of the first poly-silicon layer 24 is arranged in one area, and the resistor 14 and the capacitor 16 are arranged in the other area. Thus, the pickup ring forms two areas, one for the transistor 12 and the other for the resistor 14 and the capacitor 16. In FIG. 3, the transistor 12 is formed with eight bars of the first poly-silicon layer 24, and similarly, the pickup ring forms two areas, one for the transistor 12 and the other for the resistor 14 and the capacitor 16.
In conclusion, when the IC product is processed with the continued scaling-down of the dimensions, it is more susceptible to damage from ESD. To improve the ESD robustness of the IC product, enlarging the area of the ESD protection device provides a simple solution, but this always results in an increased layout area and a reduced integration.